Flip Flops and Clocks with Verilog in Quartus/Terasic DE2-115
6.1 هزار بار بازدید -
6 سال پیش
-
Design and simulation of a
Design and simulation of a flip flop in Verilog using Intel Quartus for the Terasic DE2-115 board. Includes writing a Verilog testbench. Prepared by teaching assistant Tyler Kehne for University of Notre Dame CSE 20221 Digital Logic Design.
6 سال پیش
در تاریخ 1397/07/01 منتشر شده
است.
6,175
بـار بازدید شده