EEPROM Programming - Address Data Control Registers ATMega328 Arduino
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Almost all AVR microcontrollers have internal EEPROM for semi-permanent data storage. Like flash memory, EEPROM can maintain its contents when electrical power is removed. The ATmega328/P contains 1K bytes of EEPROM memory. EEPROM stands for Electronically Erasable Programmable Read Only Memory which is a type of non-volatile memory used in various electronic devices to store relatively small amount of data. The EEPROM allows the data to be read, written and erased on byte level. In most variants of the AVR architecture, this internal EEPROM memory is not mapped to the addressable memory space. It can be accessed as an external peripheral device using special registers using read/write instructions, which makes EEPROM access much slower than the data or program memory.
The AVR CPU core uses three I/O registers to interact with the EEPROM. These are EEPROM address registers high and low EEARH & EEARL. The EEDR - EEPROM data register and EECR - EEPROM control register. Let's look into the details of these registers.
EEARH and EEARL are the two registers used to address the byte location in the EEPROM memory space. The ATMega328 uC has 1KiloByte of EEPROM memory, so the lower 10-bits of the register pair is used for addressing. The rest of bits from bit 11 to bit 15 are unused. The initial value of these registers are undefined and must be written with correct address value before accessing the memory. The offset of EEARH & EEARL is 42 & 41 in hex respectively. This offset is used with Load/store instructions. The offsets 22 & 21 in hex should be used when accessing the register in I/O mode that is when the registers are used with IN/OUT instructions.
In write operation, the register EEDR must be initialized with the data to be written to the EEPROM memory. After the register is loaded, instruction is issued to transfer the data from the EEDR register to EEPROM memory at the address specified by the address Register pai. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM memory. The offset of the register is 40 in hex and the hex value of 20 should be used for I/O mode.
The register EECR is used to specify the operation to be performed on the EEPROM memory. The offset of 3F in hex is used to access the control register while using LOAD/STORE instruction. And the offset 1F in hex in used with IN/OUT instructions. Now look into the details of each bit in the register.
The EEPROM Programming mode bits i.e. bit 5 and 4 is used to select the programming action when EEPROM Program Enable bit EEPE is set. The uC supports three different programming operations. Writing the bits with 00 causes the EEPROM to be erased and written with new data in an atomic operation. This programming mode takes 3.4 milliseconds to complete the operations. The erase only operation is triggered by setting 01 to these bits. And, the value 10 triggers the write only operation. The individual erase and write operation takes 1.8 milliseconds each. The write to EEPM bit is ignored when EEPE bit is set.
Writing 1 to EERIE enables the EEPROM Ready Interrupt if the I bit in the status register is set. Writing 0 to EERIE disables the interrupt. The EEPROM Ready interrupt is generated consciously when EEPE is cleared. This is an important consideration while designing the interrupt based EEPROM driver.
The EEPROM Master Program Enable i.e. EEMPE bit determines whether writing 1 to EEPE causes the EEPROM to be written. When EEMPE is '1', setting EEPE within four clock cycles writes data to the EEPROM at the selected address. If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to '1' by software, hardware clears the bit to zero after four clock cycles.
The EEPROM Write Enable Signal EEPE is the write strobe to the EEPROM. When address and data are correctly set up, the EEPE bit must be written logic '1' to write the data into the EEPROM. The EEMPE bit must be written to '1' before EEPE is written to '1', otherwise write operation does not take effect.
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the address Register, the EERE bit must be written with logic '1' to trigger the read operation. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed.
The EEPE bit must be polled before initiating the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the address Register.
Almost all AVR microcontrollers have internal EEPROM for semi-permanent data storage. Like flash memory, EEPROM can maintain its contents when electrical power is removed. The ATmega328/P contains 1K bytes of EEPROM memory. EEPROM stands for Electronically Erasable Programmable Read Only Memory which is a type of non-volatile memory used in various electronic devices to store relatively small amount of data. The EEPROM allows the data to be read, written and erased on byte level. In most variants of the AVR architecture, this internal EEPROM memory is not mapped to the addressable memory space. It can be accessed as an external peripheral device using special registers using read/write instructions, which makes EEPROM access much slower than the data or program memory.
The AVR CPU core uses three I/O registers to interact with the EEPROM. These are EEPROM address registers high and low EEARH & EEARL. The EEDR - EEPROM data register and EECR - EEPROM control register. Let's look into the details of these registers.
EEARH and EEARL are the two registers used to address the byte location in the EEPROM memory space. The ATMega328 uC has 1KiloByte of EEPROM memory, so the lower 10-bits of the register pair is used for addressing. The rest of bits from bit 11 to bit 15 are unused. The initial value of these registers are undefined and must be written with correct address value before accessing the memory. The offset of EEARH & EEARL is 42 & 41 in hex respectively. This offset is used with Load/store instructions. The offsets 22 & 21 in hex should be used when accessing the register in I/O mode that is when the registers are used with IN/OUT instructions.
In write operation, the register EEDR must be initialized with the data to be written to the EEPROM memory. After the register is loaded, instruction is issued to transfer the data from the EEDR register to EEPROM memory at the address specified by the address Register pai. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM memory. The offset of the register is 40 in hex and the hex value of 20 should be used for I/O mode.
The register EECR is used to specify the operation to be performed on the EEPROM memory. The offset of 3F in hex is used to access the control register while using LOAD/STORE instruction. And the offset 1F in hex in used with IN/OUT instructions. Now look into the details of each bit in the register.
The EEPROM Programming mode bits i.e. bit 5 and 4 is used to select the programming action when EEPROM Program Enable bit EEPE is set. The uC supports three different programming operations. Writing the bits with 00 causes the EEPROM to be erased and written with new data in an atomic operation. This programming mode takes 3.4 milliseconds to complete the operations. The erase only operation is triggered by setting 01 to these bits. And, the value 10 triggers the write only operation. The individual erase and write operation takes 1.8 milliseconds each. The write to EEPM bit is ignored when EEPE bit is set.
Writing 1 to EERIE enables the EEPROM Ready Interrupt if the I bit in the status register is set. Writing 0 to EERIE disables the interrupt. The EEPROM Ready interrupt is generated consciously when EEPE is cleared. This is an important consideration while designing the interrupt based EEPROM driver.
The EEPROM Master Program Enable i.e. EEMPE bit determines whether writing 1 to EEPE causes the EEPROM to be written. When EEMPE is '1', setting EEPE within four clock cycles writes data to the EEPROM at the selected address. If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to '1' by software, hardware clears the bit to zero after four clock cycles.
The EEPROM Write Enable Signal EEPE is the write strobe to the EEPROM. When address and data are correctly set up, the EEPE bit must be written logic '1' to write the data into the EEPROM. The EEMPE bit must be written to '1' before EEPE is written to '1', otherwise write operation does not take effect.
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the address Register, the EERE bit must be written with logic '1' to trigger the read operation. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed.
The EEPE bit must be polled before initiating the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the address Register.
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