Jitter in Wireline and Data Converter Applications Presented by Nicola Da Dalt
9.3 هزار بار بازدید -
4 سال پیش
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Abstract:This talk will discuss the
Abstract:
This talk will discuss the fundamental, first-order aspects of jitter in wireline and data converters applications. The wireline part will focus mainly on the operation of a classical Clock and Data Recovery unit and will analyze the concepts of Jitter Generation, Jitter Transfer and Jitter Tolerance. The data converter part will first describe the effect of jitter on DACs and how to calculate the resulting SNR. Subsequently, the effect of jitter on basic operation of Nyquist ADCs, Sigma Delta ADCs, and the resulting performance degradation will be covered.
Bio:
Nicola Da Dalt received the M.S. degree from the University of Padova, Italy, in 1994 and the Ph.D. degree from RWTH Aachen, Germany, in 2007, both in electrical engineering, with distinction. From 1996 to 1998 he was with CSELT, Turin, Italy, as a concept engineer for architectures and synchronization of data transmission networks. From 1998 to 2015 he was with Infineon Technologies, Villach, Austria, as Lead Principal engineer for analog mixed-signal design, and manager of the Clock and Interface Systems group. From 2015 to 2018 he was with the Programmable Solution Group of Intel Corporation, San Jose, California, as Analog Engineering Manager for the development of high-speed serial interfaces for FPGA applications. Since 2018 he has been with AMD, Santa Clara, California as Silicon Design Engineering Director, focusing on high-speed wireline transceivers. Dr. Da Dalt served on the Wireline Subcommittee of the ISSCC from 2011 to 2015. He is the recipient of the 2010 IEEE Transactions on Circuits and Systems Guillemin-Cauer Best Paper Award for his pioneering work on digital bang-bang PLLs, and the recipient of the 2017 ISSCC Outstanding Forum Speaker Award. He is co-author of the book “Understanding Jitter and Phase Noise – A Circuits and Systems Perspective”, Cambridge University Press. He has co-authored over 30 journal and conference papers and 12 granted patents.
This talk will discuss the fundamental, first-order aspects of jitter in wireline and data converters applications. The wireline part will focus mainly on the operation of a classical Clock and Data Recovery unit and will analyze the concepts of Jitter Generation, Jitter Transfer and Jitter Tolerance. The data converter part will first describe the effect of jitter on DACs and how to calculate the resulting SNR. Subsequently, the effect of jitter on basic operation of Nyquist ADCs, Sigma Delta ADCs, and the resulting performance degradation will be covered.
Bio:
Nicola Da Dalt received the M.S. degree from the University of Padova, Italy, in 1994 and the Ph.D. degree from RWTH Aachen, Germany, in 2007, both in electrical engineering, with distinction. From 1996 to 1998 he was with CSELT, Turin, Italy, as a concept engineer for architectures and synchronization of data transmission networks. From 1998 to 2015 he was with Infineon Technologies, Villach, Austria, as Lead Principal engineer for analog mixed-signal design, and manager of the Clock and Interface Systems group. From 2015 to 2018 he was with the Programmable Solution Group of Intel Corporation, San Jose, California, as Analog Engineering Manager for the development of high-speed serial interfaces for FPGA applications. Since 2018 he has been with AMD, Santa Clara, California as Silicon Design Engineering Director, focusing on high-speed wireline transceivers. Dr. Da Dalt served on the Wireline Subcommittee of the ISSCC from 2011 to 2015. He is the recipient of the 2010 IEEE Transactions on Circuits and Systems Guillemin-Cauer Best Paper Award for his pioneering work on digital bang-bang PLLs, and the recipient of the 2017 ISSCC Outstanding Forum Speaker Award. He is co-author of the book “Understanding Jitter and Phase Noise – A Circuits and Systems Perspective”, Cambridge University Press. He has co-authored over 30 journal and conference papers and 12 granted patents.
4 سال پیش
در تاریخ 1399/04/23 منتشر شده
است.
9,303
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