VLSI Physical Design with Timing Analysis

The course covers all the steps of VLSI Physical design flow needed for VLSI chip design. It includes all the steps of VLSI Physical design such as partitioning, chip planning, placement, Routing, and finally Clock routing. As the timing of digital circuits is important, two weeks will be completely dedicated to Static Timing Analysis (STA). A demo of several Open-source tools such as Qflow, Yosys, OpenSTA, and OpenROAD is also included in the course.

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