Design Verification - An Introduction

Modern SoC design relies on IP reuse. Integrating pre-verified IP into an SoC reduces the overall design effort. But design reuse also poses new challenges to the verification engineer. Lack of domain knowledge and  insufficient documentation about the IP can lead to bugs in design integration. In this short web-training, we will discuss the importance of functional verification and the challenges it poses.  We will bring out the difference between verification, validation, and testing through a simple analogy.  We will talk about the trends in the semiconductor industry that are demanding more productivity from DV engineers. We will touch upon some of the opportunities for further R&D in the area of DV.  
Intended Audience – Students of Electronics/Computer Engineering with interest in VLSI Design
Key Words – Functional Verification, Simulation, IP Reuse