Functional Verification Demo Session

Timecode
0:00 - skip this
1:12 - Introduction
7:11 - Course starting today
13:55 - Understanding electronic systems
32:30 - VLSI design styles - ASIC, FPGA
43:29 - ASIC versus FPGA
1:7:40 - ASIC design flow
1:28:33 - VLSI front end domain flow
1:37:21 - DFT basics
1:47:18 - VLSI domain job roles
2:00:45 - Functional verification intent
2:19:17 - Training schedule
2:22:58 - Functional verification training overview
2:51:20 - Preparing for job
2:59:50 - Question and answers

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