Functional Verification Demo Session

Agenda:

Timecodes
0:00 - Agenda
3:00 - Courses starting today
10:16 - Understanding electronic systems
30:51 - VLSI design styles
40:18 - ASIC versus FPGA
56:55 - ASIC design flow
1:08:30 - Functional verification intent
1:19:45 - ASIC design flow contd
1:36:20 - VLSI design job roles
1:42:38 - Training schedule
1:45:40 - Functional verification training overview
1:58:45 - Choosing right course
2:09:35 - How to prepare for job
2:20:40 - Q&A

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• #online_vlsi_courses
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• #vlsi_online_training