AXI Stream basics for beginners! A Stream FIFO example in Verilog.

Hi, I'm Stacey, and in this video I go over the basics of the AXI stream interface.

HDLforBeginners Subreddit!
Reddit: HDLForBeginners
Github Code:
https://github.com/HDLForBeginners/Ex...
Google form to give me your feedback:
https://forms.gle/ssNwzTKiioj3RNHD9

Ending music: Faith by David van Niekerk
Faith (Ocean of Reverb Original) - Da...
I'm on discord on the r/fpga server (Discord: discord, as Stacey, come say hi and chat all things FPGA!


0:00 Intro
0:35 Interface Overview
1:19 Ready Signal
1:57 Last Signal
2:16 Ready-Valid handshake rules
3:07 Code Explanation
5:35 Simulation Explanation
7:31 A wild bug appeared!
10:30 Full Axi
11:23 Outro

Buy me a coffee to support my channel: https://www.buymeacoffee.com/fpgasfor...