VLSI enthusiast Attention! VLSI work env. | All about SoC Design engineer | Front end vs Backend |

whyRD
whyRD
21.6 هزار بار بازدید - 2 سال پیش - Learn Verilog with Practice :
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Follow Kritika @ LinkedIn: kritikarampal
Part2 : The complete GUIDE for VLSI Freshers ...

About the GUEST :
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Kritika Rampal is a Senior SoC Design Engineer at Intel India.
She is a Young Professional & STEM mentor and motivational speaker from the heart.
Ever since her childhood, She began playing with Electronics.
She fell in love with Electronics Design Engineering owing to her passion for Physics and Mathematics.
She started her professional career with Cypress Semiconductor (now Infineon Technologies) as a Design Engineer and worked on the Frontend SoC Design - RTL Design, Lint, Clock Domain Crossing (CDC), Timing Constraints, Synthesis, UPF, and ECOs. She has contributed significant productivity improvement through process automation using TCL & Perl in IP Integration into the SoC timeline.
Currently, working in Intel India as Senior SoC Design Engineer, working on Frontend Low Power Challenges across Client, Server, and IoT SoCs.
To know more about her you can follow her on The LinkedIn
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About myself: Hi, I am Rajdeep Mazumder,I done my MTech from IIT Delhi in Radiofrequency design and technology. Presently I am working as a hardware engineer with Intel. I am an engineering enthusiast daily meditator and want to build hardcore engineering teaching as my profession.
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Time Stamps
00:00. Introduction
01:00 Icebreaker
02:00 Things which can disappoint Freshers in VLSI!
06:41 What is the SoC design engineer's role in VLSI
08:17 How to prepare for SoC design Engineer?
09:23 VLSI front end vs Back end.
12:56 How to choose your profile in the VLSI industry?
27:18 Build up for PART 2: Mistake A Fresher do?
17:53 Why should you subscribe to whyRD?


























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2 سال پیش در تاریخ 1401/03/15 منتشر شده است.
21,675 بـار بازدید شده
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