Power Efficient 4-bit Flash ADC using Cadence Virtuoso

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IJERTV10IS030188
Power Efficient 4-bit Flash ADC using Cadence Virtuoso

Nirali Hemant Patel

Analog-to-Digital Converters (ADCs) are useful building blocks in many applications like a biomedical, data storage read channel and an optical receiver because they represent the interface between the important world analog signal and therefore the digital signal processors. During this paper, an attempt is formed to style Power efficient 4-bit Flash Analog to Digital Converter [ADC] for Biomedical applications. Moreover, this paper describes the study of sample and hold circuit, comparator and encoder in 4-bit Flash Analog to Digital Converter (ADC) to get a power efficient ADC. During this paper, R-2R ladder is replaced with sample and hold circuit to reduce the power consumption, the traditional comparator is replaced with a simple comparator and therefore the priority encoder is employed as the alternative for the traditional encoder. It's implemented using 0.18m CMOS technology. Generally, the CADENCE VIRTUOSO tools are used for drawing the schematics and to do the simulations. The simulation results include 1.8V analog input range at a frequency of 33.20MHz.

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• #ijert
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• #4_bit_flash_adc
• #cadence_virtuoso