Low Power Verification of ARM CPU Sub-System using IEEE 1801

Recorded at: Verification Futures Conference, India
Date: 13 May 2014
Presenters: Amit Chhabra
                  Varun Aggarwal
Title: Low Power Verification of ARM CPU Sub-System using IEEE 1801

Modern day CPU subsystems need to support very high speed and ultra-low power at the same time, to have adequate user experienceand longer battery life respectively. This is achieved by deploying multiple low power techniques like dynamic voltage and frequency scaling (DVFS), body voltage modulation (body biasing), shutdown, retention, etc. which in turn manifest themselves as a new dimension in design verification in context of power intent, powersequences,states, et al. This paper describes low power simulation based techniques to verify power intent (IEEE1801-UPF2.0) and power sequences in tandem with power management IPs like power switches, power controllers, body bias IPs, etc. in ARM based CPU subsystem design.