Digital Clock, FPGA Seven Segment Interface, Verilog Code - Design Examples, Logic Design Lec 19/26
16 هزار بار بازدید -
8 سال پیش
-
Topics Covered:- (
Topics Covered:
- (0:00) Review of hours and minutes part design of digital clock
- (5:03) Design of interface with Nexys 3 FPGA's seven segments display
- (31:24) Administrative and project related discussion
- (39:23) Overview about how to start coding
- (42:48) Verilog Code of Digital Clock
- (1:02:51) Verilog Code of Digital Clock. Audio went off, subtitles added for that part
- (1:19:14) Verilog Code of Digital Clock. Audio back on
- Some Tips and Tricks using Notepad++ along the way
You can download clock code and ucf from here
http://tinyurl.com/clock-verilog-code
SUBSCRIBE!
@renzymeducation
This course was taught at Abasyn University Islamabad, Fall 2016
http://www.abasynisb.edu.pk/
- (0:00) Review of hours and minutes part design of digital clock
- (5:03) Design of interface with Nexys 3 FPGA's seven segments display
- (31:24) Administrative and project related discussion
- (39:23) Overview about how to start coding
- (42:48) Verilog Code of Digital Clock
- (1:02:51) Verilog Code of Digital Clock. Audio went off, subtitles added for that part
- (1:19:14) Verilog Code of Digital Clock. Audio back on
- Some Tips and Tricks using Notepad++ along the way
You can download clock code and ucf from here
http://tinyurl.com/clock-verilog-code
SUBSCRIBE!
@renzymeducation
This course was taught at Abasyn University Islamabad, Fall 2016
http://www.abasynisb.edu.pk/
8 سال پیش
در تاریخ 1395/09/05 منتشر شده
است.
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